The present invention generally relates to methods of shielding low voltage devices residing on high voltage domain, and more specifically relates to using native transistors in level shifters in order to shield low voltage devices.
FIG. 1 illustrates a typical Complementary Metal-Oxide Semiconductor (CMOS) integrated circuit or chip 10, wherein an internal core 12 is surrounded by input/output (I/O) transistors 14 (hereinafter the xe2x80x9cI/Oxe2x80x9d). In recent CMOS technologies (i.e., .25UM, .18UM, .13UM), the internal core 12 of a chip 10 operates at a reduced voltage compared to the I/O 14. As a result, the internal core 12 burns less power (CMOS power is proportional to Vdd2), and transistors in the core 12 can be scaled to smaller dimensions. Typically, digital signals in the core 12 (which is most of the chip 10) are at 0 or VDDCORE, while digital signals in the I/O 14 (the smaller portion of the chip 10) are at 0 or VDDIO. As a result of the voltage difference, level shifters 16 are needed between the core 12 and the I/O 14 in order to translate digital signals from one voltage level to the other.
FIGS. 2 and 3 illustrate two traditional level shifter circuits. In FIGS. 2 and 3, xe2x80x9cTOxe2x80x9d refers to a voltage tolerant (xe2x80x9cthick oxidexe2x80x9d) I/O transistor, while xe2x80x9cHPxe2x80x9d refers to a low voltage (xe2x80x9chigh performancexe2x80x9d) core transistor. While FIG. 2 illustrates a signal-to-gate MOS (Metal-Oxide Semiconductor) level shifter, FIG. 3 illustrates a signal-to-source MOS (Metal-Oxide Semiconductor) level shifter. As shown in both FIGURES, both level shifters provide that VDDCORE (1.2V or 1.0V) is put on the gate of a voltage tolerant device (because that device""s drain may go to VDDIO). As core voltages are scaled to 1.2V or even 1.0V or 0.8V, these implementations are becoming very slow, big, and in some cases, simply do not function. Additionally, VDDCORE is getting too close to the voltage threshold of the voltage tolerant device.
FIGS. 4 and 5 illustrate a common proposed solution, wherein FIG. 4 corresponds to FIG. 2, and FIG. 5 corresponds to FIG. 3. As shown, the common proposed solution is to place a voltage regulator network in the circuit, and then use core devices 22 as the switching elements. The voltage regulator network 20 consists of voltage tolerant transistors 24, each having a reference voltage (xe2x80x9cVREFxe2x80x9d) on its gate. The reference voltage is selected to insure that the drain of the switching devices 22 cannot exceed VDDCORE.
The implementation shown in FIGS. 4 and 5 provides some disadvantages. With regard to performance, the backbiased voltage threshold of the regulator transistors 24 varies over temperature, VREF and process. Additionally, the reference voltage, VREF, has a similar variability. All of the variations must be taken into account when designing the circuit, thus nominal performance must be degraded. Furthermore, the reference generator (which generates VREF) draws direct current (DC) power. Hence, in order to avoid routing high voltage signals in the core, a VREF generator must be implemented into every I/O function, and the reference generators consume silicon area. The voltage reference (VREF) must be greater than VDDCORE (i.e., VDDCORE+VTLIN) because the voltage regulator devices 24 have such high voltage thresholds.
A general object of an embodiment of the present invention is to shield low voltage devices residing on high voltage domain.
Another object of an embodiment of the present invention is to use native transistors in level shifters in order to shield low voltage devices residing on high voltage domain.
Still another object of an embodiment of the present invention is to shield low voltage devices residing on high voltage domain without having to use a reference voltage.
Yet another object of an embodiment of the present invention is to shield low voltage devices residing on high voltage domain by using VDDCORE on the gate of a voltage tolerant, native device.
Briefly, and in accordance with at least one of the forgoing objects, an embodiment of the present invention provides a level shifter circuit configured for use between a core of a chip and input/output transistors of the chip in order to shield low voltage devices residing on the core. The level shifter circuit includes voltage tolerant native devices which have VDDCORE on their gates, and each voltage tolerant native device is cascoded with a low voltage transistor on the core.